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SAA7388 Error correction and host interface IC for CD-ROM (ELM)
Preliminary specification File under Integrated Circuits, IC01 1996 Apr 26
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 .10 8 9 10 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 12 13 14 15 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION CD-DSP interface and data input Error correction and EDC check Host interface Subcode channel Q-to-W buffering External buffer memory Sub-CPU registers Register Descriptions Sub-CPU interface Host registers CD-DSP Timings LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS TIMING CHARACTERISTICS Q-to-W subcode interface timing External memory SRAM timing External memory DRAM timing Sub-CPU interface timing ATAPI host interface timing SANYO compatibility mode host interface timing Oak compatibility mode host interface timing Crystal oscillator PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS
SAA7388
1996 Apr 26
2
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
1 FEATURES 2 GENERAL DESCRIPTION
SAA7388
* CD-ROM (Mode 1) and CD-I (Mode 2 - Form 1 and Form 2) formats supported * Real-time error detection and correction in hardware * Suitable for octal speed, n = 8. * Maximum host transfer burst rate of 13.3 Mbyte/s * Corrects two errors per symbol with erasure correction * 36 kbit of on-chip error correction buffer RAM * 12-byte command FIFO and 12-byte status FIFO * Compatible with the Advanced Technology Attachment (ATA) register set and the Advanced Technology Attachment Program Interface (ATAPI) command set * Operates with popular memories. (up to 128 kbyte SRAM; 1 to 16 Mbit DRAM, different speed grades, nibble or byte wide) * Interface to Integrated Drive Electronics (IDE) bus without external bus drivers * Q-to-W subcode buffering, de-interleaving and correction are supported * Device can operate with audio RAMs. A RAM test allows bad segments to be identified. 3 QUICK REFERENCE DATA SYMBOL VDDD1 VDDD2 IDDD fclk Tamb Tstg 4 PARAMETER digital supply voltage 1 digital supply voltage 2 supply current clock frequency operating ambient temperature storage temperature
The SAA7388 decoder is a block decoder buffer manager for high-speed CD-ROM applications that integrates real-time error correction and detection and host interface data transfer functions into a single chip. The SAA7388 has an on-chip 36-kbit memory. This memory is used as a buffer memory for error and erasure corrections. The chip also has a buffer memory interface thus enabling the connection of SRAM up to 128 kbytes, or DRAM up to 16 Mbits. The on-chip memory is sufficient to buffer 1 sector of data. The external memory can buffer many more, depending on memory size. The error corrector of the SAA7388 can perform 2-pass error correction in real-time. Buffer memory for this correction is integrated on-chip. The SAA7388 has an host interface that is compatible with the SANYO LC89510 or OAK OTI-012 and also compatible with the ATA/IDE/ATAPI hard disc interface bus. (All ATAPI registers are present in hardware). Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
MIN. 3.0 4.5 - 15.2 0 -55 5
TYP. 3.3 60 48 - -
MAX. 3.6 5.5 - 50.4 +70 +125 V V
UNIT
mA MHz C C
ORDERING INFORMATION PACKAGE
TYPE NUMBER NAME SAA7388GP QFP80 DESCRIPTION plastic quad flat package; 80 leads; lead length 1.95 mm; body 14 x 20 x 2.8 mm VERSION SOT318-2
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
5 BLOCK DIAGRAM
SAA7388
handbook, full pagewidth
RCK DGND VDDD2 50, 74 SFSY 28 SUB 29
BCK WS 31
DATA C2PO 34 35 TEST2 23 TEST1 25
1, 14, 24, 41, 59, 68 32
30
33
VDDD1
DECODER SERIAL INTERFACE
TEST
SDA SCL INT RESET SYN
36 75-80 37 38 39 40 MICROCONTROLLER INTERFACE ERROR CORRECTOR RA0 to RA5
SAA7388
MEMORY MANAGER
2-10 RA6 to RA14 12 11 13 15-22 RA16/CAS RA15/RAS RWE RD0 to RD7
SRAM CACHE
DMACK DA1 DA2/EJECT CS2/SELRQ IOCS16
45 70 71 72 73 OSCILLATOR HOST INTERFACE 27 26
CRIN CROUT
42 CS1/HEN
43
44
69
46
47
48
49
51-58
60-67
MGD305
HRD
DMARQ/DTEN SCRST/STEN
HWR DA0/CMD
HD0 to HD7 HD8 to HD15
IRQ/EOP/HFBC
IORDY/WAIT/HFBLB
Fig.1 Block diagram.
1996 Apr 26
4
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
6 PINNING SYMBOL DGND1 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15/RAS RA16/CAS RWE DGND2 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 TEST2 DGND3 TEST1 CROUT CRIN SFSY RCK SUB BCK VDDD1 WS DATA C2PO SDA SCL INT RESET SYN 1996 Apr 26 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O - O O O O O O O O O O O O - I/O I/O I/O I/O I/O I/O I/O I/O I - I O I I O I I - I I I I/O I O I I digital ground 1 buffer RAM address bus output line 6 buffer RAM address bus output line 7 buffer RAM address bus output line 8 buffer RAM address bus output line 9 buffer RAM address bus output line 10 buffer RAM address bus output line 11 (SRAM) only buffer RAM address bus output line 12 (SRAM) only buffer RAM address bus output line 13 (SRAM) only buffer RAM address bus output line 14 (SRAM) only DESCRIPTION
SAA7388
buffer RAM address bus output line 15 (SRAM) or RAS (DRAM) buffer RAM address bus output line 16 (SRAM) or CAS (DRAM) buffer RAM write enable output digital ground 2 buffer RAM data bus bidirectional line 0 buffer RAM data bus bidirectional line 1 buffer RAM data bus bidirectional line 2 buffer RAM data bus bidirectional line 3 buffer RAM data bus bidirectional line 4 buffer RAM data bus bidirectional line 5 buffer RAM data bus bidirectional line 6 buffer RAM data bus bidirectional line 7 test input 2 digital ground 3 test input 1 clock oscillator output clock oscillator input serial subcode input frame sync input serial subcode clock output (active LOW) serial input for Q-to-W subcode input serial interface bit clock input digital supply voltage 1 (3.3 V) serial interface word clock input serial data input serial interface flag input sub-CPU serial data input/output sub-CPU serial clock input sub-CPU open-collector interrupt output power-on reset input (active LOW) sync signal input from sub-CPU 5
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL DGND4 CS1/HEN HWR HRD DMACK IORDY/WAIT/HFBLB SCRST/STEN DMARQ/DTEN IRQ/EOP/HFBC VDDD2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 DGND5 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 DGND6 DA0/CMD DA1 DA2/EJECT CS2/SELRQ IOCS16 VDDD2 RA0 RA1 RA2 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 I/O - I I I I O O O O - I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - I I I I O - O O O digital ground 4 host interface enable input (active LOW) host interface write enable input (active LOW) host interface read enable input (active LOW) DMA acknowledge input host interface wait output (active LOW); 3-state control DESCRIPTION
SAA7388
host interface status enable output ATAPI sub-CPU reset signal (active LOW) ATAPI DMA request host interface data enable output (active LOW); 3-state control host interface end of process flag output ATAPI host interrupt request (active LOW); 3-state control digital supply voltage 2 (5 V) host interface data bus input/output line 0 host interface database input/output line 1 host interface database input/output line 2 host interface data bus input/output line 3 host interface data bus input/output line 4 host interface data bus input/output line 5 host interface data bus input/output line 6 host interface data bus input/output line 7 digital ground 5 host interface data bus input/output line 8 host interface data bus input/output line 9 host interface data bus input/output line 10 host interface data bus input/output line 11 host interface data bus input/output line 12 host interface data bus input/output line 13 host interface data bus input/output line 14 host interface data bus input/output line 15 digital ground 6 host interface data input (active LOW)/command select input host interface address line 0 ATAPI address line input 1 ATAPI address line input 2 ATAPI chip select input 2 ATAPI 16-bit data select output digital supply voltage 2 (5 V) buffer RAM address bus output line 0 buffer RAM address bus output line 1 buffer RAM address bus output line 2
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL RA3 RA4 RA5 PIN 78 79 80 I/O O O O DESCRIPTION buffer RAM address bus output line 3 buffer RAM address bus output line 4 buffer RAM address bus output line 5
SAA7388
72 CS2/SELRQ
69 DA0/CMD
handbook, full pagewidth
73 IOCS16
71 DA2/EJECT
68 DGND6
74 VDDD2
67 HD15
66 HD14
DGND1 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13
65 HD13
77 RA2
76 RA1
75 RA0
70 DA1
80 RA5
79 RA4
78 RA3
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53
HD12 HD11 HD10 HD9 HD8 DGND5 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 VDDD2 IRQ/EOP/HFBC DMARQ/DTEN SCRST/STEN IORDY/WAIT/HFBLB DMACK HRD HWR CS1/HEN DGND4
RA14 10 RA15/RAS 11 RA16/CAS 12
SAA7388
RWE 13 DGND2 14 RD0 15 RD1 16 RD2 17 RD3 18 RD4 19 RD5 20 RD6 21 RD7 22 TEST2 23 DGND3 24 TEST1 25 CROUT 26 CRIN 27 SFSY 28 RCK 29 SUB 30 BCK 31 VDDD1 32 WS 33 DATA 34 C2PO 35 SDA 36 SCL 37 INT 38 RESET 39 SYN 40 52 51 50 49 48 47 46 45 44 43 42 41
MGD306
Fig.2 Pin configuration.
1996 Apr 26
7
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
6.1 6.1.1 Pin functions RA0 TO RA14 6.1.12 C2PO
SAA7388
External memory address signals. 6.1.2 RA16/CAS
Error flag from the CD decoder. A HIGH indicates that a byte has not been corrected by the C2 error corrector and therefore is not valid. This is taken into account by the SAA7388 error corrector. 6.1.13 SDA
External memory RA16 signal if SRAM or, CAS signal if DRAM. 6.1.3 RA15/RAS
Sub-CPU bidirectional data signal. This signal forms part of the 3-wire serial interface between the SAA7388 and the sub-CPU. 6.1.14 SCL
External memory RA15 signal if SRAM or, RAS signal if DRAM. 6.1.4 RWE
Write output enable signal for external buffer memory. This is LOW when the SAA7388 wants to write data into the external memory. 6.1.5 RD0 TO RD7
Sub-CPU sync signal. This signal forms part of the 3-wire serial interface between the SAA7388 and the sub-CPU. This signal is used to synchronize data transfers between the sub-CPU and the SAA7388. 6.1.15 INT
External buffer memory bidirectional data signals. 6.1.6 SFSY
Sub-CPU interrupt signal. This active LOW output signals to the sub-CPU that the SAA7388 has an interrupt request. 6.1.16 RESET
Frame sync for the Q-to-W subcode, indicates when P-channel is available by a HIGH-to-LOW transition. Frame 0 is also indicated by no transition on this line. 6.1.7 RCK
Forcing this input LOW resets the SAA7388. 6.1.17 SYN
In response to SFSY going LOW data is clocked into the SAA7388 before each rising edge using this clock output. 6.1.8 SUB
Sub-CPU clock signal. This signal forms part of the 3-wire serial interface between the SAA7388 and the sub-CPU. This signal is the sub-CPU driven bit clock used to synchronize the signals on the SDA line. 6.1.18 CS1/HEN
Q-to-W subcode is input in response to RCK in 3-wire EIAJ mode or WS in "V4" mode compatible with the SAA7345. 6.1.9 BCK
In the ATAPI mode this is the host chip select 1 address signal. In the Sanyo and Oak compatibility modes setting this input LOW enables the host interface. 6.1.19 HWR
Bit clock for the serial data input from the CD decoder. 6.1.10 WS
This active LOW signal is the host write request. Word clock for the serial data input from the CD decoder. 6.1.11 DATA 6.1.20 HRD
This active LOW signal is the host read request. Serial data input from the CD decoder. This may be either I2S-bus or EIAJ 16-bit format.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
6.1.21 DMACK 6.1.25 IRQ/EOP/HFBC
SAA7388
This signal is used in the ATAPI and Oak compatibility modes during DMA transfers. The host pulls this signal LOW in response to a DMARQ request to indicate that it is ready to transfer data. If this signal is not being used then it must be pulled HIGH for SAA7388 to operate correctly. 6.1.22 IORDY/WAIT/HFBLB
In the ATAPI mode this active HIGH signal indicates a host interrupt request. It is asserted when the sub-CPU writes to the ITRG register and is negated when the host reads the status register or writes to the command register. In the Sanyo compatibility mode this signal is set LOW when the last data byte is transferred to or from the host. In the Oak compatibility mode this is the Host First Byte Cycle output and is HIGH while the first byte in the pseudo 16-bit DMA transfer is accessed. It should be used to inhibit non-DMA transactions while the first byte is latched. 6.1.26 HD0 TO HD15
In the ATAPI mode this signal is negated to extend the host transfer cycle of any host register access. It is used in PIO transfers. When IORDY is not negated it is in a high-impedance state. In the Sanyo compatibility mode the function of this signal depends on the SELRQ input. If SELRQ is HIGH then WAIT is set LOW to extend the host transfer cycle. If SELRQ is LOW then WAIT acts as the DRQ signal in a DMA transfer. In the Oak compatibility mode this signal is the Host First Byte Latch signal. A rising edge on this signal is used to latch the first byte in a pseudo 16-bit DMA read. HFBLB can only be HIGH when pseudo 16-bit DMA transfer mode is selected. 6.1.23 SCRST/STEN
These are the bidirectional Host Data signals. In the Sanyo and Oak compatibility modes HD8 to HD15 are never used. 6.1.27 DA0/CMD
In the ATAPI mode this is the host Data Address 0 signal. In the Sanyo and Oak compatibility modes this input selects between command or data transfers. 6.1.28 DA1
This is the ATAPI Data Address 1 signal. 6.1.29 DA2/ EJECT
In the ATAPI or Oak compatibility mode this signal is pulled LOW to reset the sub-CPU in response to a reset command from the host. In the Sanyo compatibility mode this signal is pulled LOW to signal to the host that status bytes are available for transfer. 6.1.24 DMARQ/DTEN
In the ATAPI mode this is the Data Address 2 signal. In the Oak compatibility mode this is the door switch input pin. Its state is reflected in the TSTAT register. 6.1.30 CS2/SELRQ
In the ATAPI or Oak compatibility mode this signal is asserted when the SAA7388 is ready to transfer data between the host and itself. In ATAPI single word and Oak DMA transfers this occurs at every word. In ATAPI multi-word DMA transfers this occurs at the start of the transfer. In the Sanyo compatibility mode this signal is pulled LOW to signal to the host that data bytes are available for transfer.
In the ATAPI mode this is the Chip Select 2 signal. In the Oak and Sanyo compatibility mode this is the data transfer mode select input. It is used to select between PIO and DMA transfers. 6.1.31 IOCS16
This open-collector signal is used in the ATAPI mode to signal to the host that a 16-bit data port has been addressed. It is not activated during DMA transfers.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7 FUNCTIONAL DESCRIPTION 7.3 Host interface
SAA7388
The SAA7388 is comprised of four main blocks; a CD player interface, an error corrector, a host interface and a memory manager. These four blocks operate in parallel. All receive and send data to the buffer memory via the memory manager. A 36-kbit on-chip SRAM has been incorporated to allow high-speed data read operations for the error corrector. The SAA7388 performs simultaneous data input buffering, error correction and host data transfer. 7.1 CD-DSP interface and data input
The host interface controls data transfers between the SAA7388 and an external microcontroller. The host interface can be programmed to operate in three modes. In the Sanyo compatibility mode the host interface is functionally compatible with the Sanyo LC89510 block decoder. In the Oak compatibility mode the host interface is functionally compatible with the Oak OTI-012 controller chip in enhanced mode. In the ATAPI mode the interface meets the ATA Program Interface specification. 7.4 Subcode channel Q-to-W buffering
The input data is synchronized, decoded, and written to the buffer RAM. The input data format is software programmable. The synchronization is achieved using a sync detector and a sync interpolator. The sync detector detects the sync pattern in every sector while the interpolator avoids sync loss when no sync is found. The detector and interpolator can be individually enabled and disabled under software control. After decoding, each full sector of data (2352 bytes) comprising sync, header, sub-header and parity fields is written to the buffer RAM. 7.2 Error correction and EDC check
As well as buffering the main data, the SAA7388 can also be used to buffer R-to-W subcode data in buffer memory. Two buffer modes exist, raw mode and cooked mode. In the raw mode, data is written to an external RAM without any processing being performed. In the cooked mode, the Q-channel data is extracted, the Q-channel CRC is calculated, the R-to-W data is de-interleaved and the residues of each R-to-W frame are calculated. These residues make it easier to correct errors in the data. 7.5 External buffer memory
Error correction and detection is performed on each sector after it is written to the buffer RAM. The SAA7388 buffers flag and data of sectors to be corrected in a 9-bit, 4096 words on-chip RAM memory. For erasure correction, no external 9-bit memory is required. The standard error correction algorithm can be programmed, and supports mode 1 and mode 2 form 1 and form 2 discs. After error correction, an electronic data check is executed. When this EDC check is also complete, the sector header and sub-header is written to 8 header registers, and a decode complete interrupt is generated. The microcontroller can then read the decoder status, the sector header and sub-header and the sector start address from the SAA7388.
It is possible to use the SAA7388 with different external RAM memories. From 0 to 128 kbyte SRAMs or to 16-Mbit DRAMs are possible. Memories may be nibble or byte wide (allowing 2, 8 or 16 Mbits). Selection is performed under software control. Unique to the SAA7388 is its ability to work with partly defective DRAMs. The SAA7388 offers the possibility to use a DRAM with bytes in error. A RAM test is executed under microcontroller control. This RAM test indicates defective segments to the microcontroller which keeps a list of which bad sectors to avoid. The list can be stored in the buffer memory and/or the microcontrollers own memory. 7.6 Sub-CPU registers
This section describes the registers in the SAA7388. The operation of the registers varies depending on whether they are being read from or written to, and the host mode selected.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 1 # 0 1 2 3 4 5 6 7 8 9 Sub-CPU registers during write NAME ADATA/ SBOUT IFCTRL DBCL DBCH DACL DACH DTRG DTACK WAL WAH CTRL0 CTRL1 PTL PTH RESET DACHH WAHH PTHH SUB_L SUB_H INCNF MEMS ASTAT ITRG ASAMT DTCTR ADRSEL AINTR AERR res. DMAMODE UDMA IISmode 0 div 1 PRIORITY mem DECEN SYIEN lookahead SYDEN CMDIEN DTEIEN BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
SAA7388
AR 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001
BIT 1
BIT 0
ATAPI Data register/Status Byte Output register DECIEN CMDBK DTWAI STWAI DOUTEN SOUTEN
Data Byte Count register bits 7 to 0 Data Byte Count register bits 15 to 8 Data Address Counter register bits 7 to 0 Data Address Counter register bits 15 to 8 Data Transfer Trigger register Data Transfer Acknowledge register Write Address register bits 7 to 0 Write Address register bits 15 to 8 E01RQ AUTOQ ERAMRQ MODRQ WRRQ ECCRQ ENCODE DSCREN COWREN FORMRQ MBCKRQ SHDREN
10 01010 11 01011 12 01100 13 01101 14 01110 15 01111 16 10000 17 10001 18 10010 19 10011 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 27 11011 28 11100 29 11101 30 11110 31 11111
Block Pointer register bits 7 to 0 Block Pointer register bits 15 to 8 reserved Write Address register bits 20 to 16 Block Pointer register bits 20 to 16 Subcode Address register bits 7 to 0 Subcode Address register bits 9 and 8 div 0 QWmode 0 QWon RFRSH QWcook WIDTH RAM test STATIC 0 CACHE HSEL
Data Address Counter register bits 20 to 16
ATAPI Status register Host Interrupt Trigger register ATAPI Drive Address register ATAPI SAM TAG register SUBIEN RDRV TRANT ATAPI Drive Select register ATAPI Interrupt Reason register ATAPI Error register
26 11010 ADRADR
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 2 # 0 1 2 3 4 5 6 7 8 9 Sub-CPU registers during read NAME APCMD/ COMIN IFSTAT DBCL DBCH HEAD0 HEAD1 HEAD2 HEAD3 PTL PTH WAL WAH STAT0 STAT1 STAT2 STAT3 PTHH WAHH SUB_L SUB_H CRCOK MINERR RMOD3 VALST ILSYNC SECERR RMOD2 CMDI DTEI BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
SAA7388
AR 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001
BIT 1
BIT 0
ATAPI packet command data/command input register DECI SUBI DTBSY SRSTI/ STBSY DTEN STEN
Data Byte Count register bits 7 to 0 Data Byte Count register bits 15 to 8 Minutes/ File Number Seconds/ Channel Number Frames/ Submode Mode/ Coding Information Block Pointer register bits 7 to 0 Block Pointer register bits 15 to 8 Write Address register bits 7 to 0 Write Address register bits 15 to 8 NOSYNC RMOD1 CBLK Block Pointer register bits 20 to 16 Write Address register bits 20 to 16 Subcode Address register bits 7 to 0 Subcode Address register bits 9 and 8 LBLK RMOD0 USHORT SH0ERR MODE SBLK SH1ERR FORM ERR SH2ERR UCEB SH3ERR BLKERR MODERR
10 01010 11 01011 12 01100 13 01101 14 01110 15 01111 16 10000 17 10001 18 10010 19 10011 20 10100 21 10101 22 10110 23 10111 24 11000 25 11001 26 11010 27 11011 28 11100 29 11101 30 11110 31 11111
RFORM1 RFORM2
HCON ACMD ASAMT ADCTR ADRSEL AINTR AFEAT
Oak Host Configuration register ATAPI Command register ATAPI SAM TAG register ATAPI Device Control register ATAPI Drive Select register ATAPI Interrupt Reason register ATAPI Features register
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7 7.7.1 Register Descriptions SBOUT/ADATA 7.7.2 COMIN/ APCMD
SAA7388
This is a 12 byte FIFO used to transfer data from the sub-CPU to the host. In the Sanyo and Oak compatibility mode writing to this register starts a status byte transfer. In this mode if the SOUTEN bit in the IFCTRL register has been set to logic 1, writing to the SBOUT register sets the STBSY bit to logic 0. If the STWAI bit is set to logic 0, STEN is immediately set LOW to inform the host computer that the status byte is ready to be read from. If the STWAI bit is set to logic 1 and the DTEN bit in the IFSTAT register is also set to logic 1, both the STEN pin and the STBSY will go LOW. However, if the STWAI bit is set to logic 0, and the DTEN bit is set to logic 0, then STEN is held HIGH until the DTEN bit goes HIGH, thereafter it goes LOW. Table 3 BIT 7 6 5 4 IFCTRL register bits NAME CMDIEN DTEIEN DECIEN CMDBK
During the ATAPI mode this register is used to read the program command sent by the host. The program command can only be received if the appropriate mode has been selected (see Table 22) and a data transfer has been started (see DTRG register). During Sanyo and Oak compatibility modes this register is a 12 byte FIFO which is used to transfer commands from the host to the sub-CPU. If reading this register empties the command FIFO then CMDI is set to logic 1 and further reads from the register will return FFH. 7.7.3 IFCTRL
The IFCTRL register provides control over the host interface. Resetting the chip will clear all bits. In the ATAPI mode, only, bits 7 to 5 have any effect.
DESCRIPTION Enable bits for CMDI, DTEI and DECI. These are interrupt masks, enabling/disabling the sub-CPU interrupt pin. They do not affect the bits in the IFSTAT register. If set to logic 1, the corresponding interrupt is enabled. It should be noted that these masks do not clear the interrupts. Command break enable. If set to logic 0 then the command break function is enabled and if the host writes to the COMIN FIFO then any data or status byte transfers in progress will be terminated. If set to logic 1 then this operation is disabled. The data transfer interrupt DTEI is not generated by a command break. Data transfer WAIT enable. Setting this bit to logic 0 enables the data WAIT function. The data WAIT function allows the SAA7388 to delay hardware execution of the data transfer until a status byte transfer has been completed. Disabling the data WAIT function allows data transfers to take place independently of status byte transfers. Status byte transfer WAIT enable. This bit acts in a similar way to the DTWAI bit except it controls the status WAIT function. The status WAIT function allows the SAA7388 to delay hardware execution of the status transfer until a data byte transfer has been completed. Disabling the data WAIT function allows status transfers to take place independently of data transfers. Data output enable. DOUTEN enables/disables data transfers. When set to logic 0, all data transfers in progress are aborted. Status output enable. SOUTEN enables/disables status byte transfers. When set to logic 0, the status FIFO register is reset to empty and all status byte transfers in progress are aborted.
3
DTWAI
2
STWAI
1 0
DOUTEN SOUTEN
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7.4 IFSTAT
SAA7388
The IFSTAT register indicates the state of the host interface. In the ATAPI mode, only bits 7 to 2 have any meaning. Table 4 BIT 7 IFSTAT register bits NAME CMDI DESCRIPTION Command interrupt. In the ATAPI mode this bit is asserted when the host has written to the ATAPI command register (see ACMD register) and the drive is selected. It is also asserted when the host writes the execute drive diagnostic command (90H) to the ATAPI command register, regardless of whether the drive is selected. It is negated when the sub-CPU reads the ACMD register. In the Sanyo and Oak compatibility modes this bit is asserted while there are command bytes waiting in the COMIN FIFO. It is negated when the COMIN FIFO is empty. Data transfer end interrupt. This bit is asserted at the end of data transfer. It is negated when the sub-CPU writes to the DTACK register. If the ATAPI mode is selected this bit is also asserted when a program command has been received and after a sub-CPU memory transfer. Decoder interrupt. This bit is asserted when a new sector is available. It is negated by reading the STAT3 register. Subcode interrupt. This bit is asserted when a new subcode is available. It is negated by reading the SUB_H register. Data transfer busy. This bit indicates if a data transfer is taking place. It is asserted by writing to the DTRG register and is negated at the end of the transfer. SRST bit interrupt/status transfer busy. In the ATAPI mode this bit is asserted when the host writes to the ATAPI device control register and sets the SRST bit. It is negated when the sub-CPU reads the ADCTR register. It should be noted that if this bit is asserted in the ATAPI mode then the sub-CPU interrupt will also be asserted. The SRSTI interrupt cannot be disabled. In the Sanyo and Oak compatibility modes this bit indicates if a status byte transfer is taking place. It is asserted by writing to the SBOUT register and is negated when the host has emptied the status FIFO. Data transfer and status transfer. These bits reflect the state of the DTEN and STEN pins in the Sanyo and Oak compatibility modes. They are updated at the end of a host read or write. 7.7.6 DACL, DACH AND DACHH
6
DTEI
5 4 3 2
DECI SUBI DTBSY SRSTI/STBSY
1 0
DTEN STEN
7.7.5
DBCL AND DBCH
The Data Byte Counter is used by the sub-CPU to control the number of bytes that are transferred in a data transfer. In the ATAPI mode all 16 bits are available while in the Sanyo and Oak compatibility modes only 15 bits are available with bit 7 of DBCH indicating the state of DTEI (see Table 4). During memory-to-host data transfers the data byte counter is decremented after every host read. During host-to-memory data transfers the data byte counter is decremented as data is written into external buffer memory.
This 21-bit write-only register is used to specify the external buffer address of the first byte of the data block to be transferred to the host. Once the address has been set, it is incremented automatically as successive bytes are transferred with the host. It should be noted that pointer operation is asynchronous from host read/write operation. For this reason, counter increments are not coincident with host transfer operations.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Bit 7 of the DACHH register specifies which memory is accessed. If the bit is clear then the address refers to the external memory, if the bit is set then the address refers to the 4 kbyte internal memory. The internal memory should not be accessed during error correction. This register should be written to before each data transfer because its value will be undefined at the end of the previous transfer. 7.7.7 PTL, PTH AND PTHH
SAA7388
for the first byte of the next sector. The new pointer value is temporarily stored in the PT register. This cannot be read after WA has been written to. 7.7.9 DTRG
Writing to this register starts a data transfer. The data written is discarded. 7.7.10 DTACK
This register holds a 21-bit pointer to the external buffer memory address of the head of the current data block after correction. The SAA7388 defines the minute byte in the header to be at the head of the block, and the 12 sync bytes at the tail of the block. Each block contained in the buffer is taken to be 2352 bytes. The controller can transfer the decoded block back to the host by copying the address of this register to the DACL, DACH and DACHH pointers after a decoder interrupt. When the WRRQ bit in the CTRL0 register is set to logic 1, this pointer is updated at the sync signal of every 2352 byte clocks. 7.7.8 WAL, WAH AND WAHH
Writing to this register clears the DTEI interrupt. The data written is discarded. 7.7.11 HEAD0, HEAD1, HEAD2 AND HEAD3
These registers are used to hold the header and the sub-header data of the current block. To read the header data set, the SHDREN bit in the CTRL1 register is set to logic 0; to read the sub-header data, SHDREN is set to logic 1. If sub-header is selected, the registers will normally hold data from bytes 20 to 23. However, if the error flag for one of these bytes is set, then the byte is taken from the first sub-header field. (bytes 16 to 19.) The error flags for header and sub-header can be read from the STAT1 register. No error correction is performed on header or sub-header. Header and sub-header registers are valid directly after decoder interrupt, and as long as the VALST bit in the STAT3 register is LOW. In all write modes they contain information on the block whose header is pointed to by PTL, PTH and PTHH.
These registers contain a 21-bit address of where raw data from the drive is written to the external buffer memory. The pointer is automatically incremented during data transfer. The pointer should only be read while drive data writes to the buffer are disabled. If WAHH is written to while drive data write is enabled, then the new WA value will be used Table 5 HEAD registers REGISTER HEAD0 HEAD1 HEAD2 HEAD3 HEAD0 HEAD1 HEAD2 HEAD3
SHDREN 0 0 0 0 1 1 1 1
CONTENTS MINUTES (byte 12) SECONDS (byte 13) FRAMES (byte 14) MODE (byte 15) FILE NUMBER (byte 16 or 20) CHANNEL NUMBER (byte 17 or 21) SUBMODE NUMBER (byte 18 or 22) CODING INFORMATION (byte 19 or 23)
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7.12 CTRL0
SAA7388
Resetting the chip sets all the bits in this register to logic 0. Table 6 BIT 7 6 CTRL0 register NAME DECEN lookahead FUNCTION Disable decoding = 0; Enable decoding = 1. This bit enables/disables decoding functions. Disabling the decoding functions also disables the decoder interrupt. At interrupt PT, header refer to current block = 0; At interrupt PT, header refer to next block = 1. When this bit is set to logic 1 at decoder interrupt, CMA and header registers will give information on the next block instead of on the current block. The lookahead mode was included to provide support for bad RAMs, and to give the CPU better control on the blocks it wants to read. Disable error correction of bytes = 0; Enable correction of CIRC mis-corrections = 1. Setting this bit to logic 0 instructs the error corrector not to correct bytes flagged as reliable by the CIRC error corrector. Disable automatic error correction = 0; Enable automatic error correction = 1. Requests automatic extraction of form bit during mode2 correction from sub-header data. Disable erasure flag use = 0; Enable erasure flag use = 1. When set to logic 1, the SAA7388 will enable the use of erasure flag information for error correction. When set to logic 0, the SAA7388 will disable the use of erasure flag information for error correction. Use of erasure flags must be disabledSAA7388 when the CD-DSP does not output erasure flags and when the internal buffer RAM is disabled (which is necessary for repeat correction). Disable data writes to the buffer and PTL updates = 0; Enables data writes to the buffer and PTL updates = 1. This bit enables/disables writes from the CD drive into the buffer. It also enables/disables pointer (PTL, PTH and PTHH) updates each time a block is received. When WRRQ is set to logic 1, data write will start from the first byte of the next block onwards. When WRRQ is set to logic 0, repeat correction is enabled. With WRRQ set to logic 0, the internal buffer RAM is disabled. Disable ECC correction = 0; Enable ECC correction = 1. When ECCRQ is set to logic 1 the blocks received by the SAA7388 will be error corrected before a decoder interrupt is generated. When ECCRQ is set to logic 0 no corrections are performed. The algorithm used is a QD, PD, QE, PE algorithm. In a first step, errors are corrected; in a second step, erasures are corrected. Correction data is read from the on-chip 36 kbit buffer memory. Normal operation = 0; Test mode, do not use = 1, this bit must always be set to logic 0.
5
E01RQ
4 3
AUTORQ ERAMRQ
2
WRRQ
1
ECCRQ
0
ENCODE
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 7 Error correction modes lookahead X 0 0 0 0 1 1 WRRQ X 0 0 1 1 1 1 ECCRQ X 0 1 0 1 0 1 monitor only repeat correction write only real-time correct, normal mode write only, lookahead real-time correct, lookahead decoder mode decoder disable; note 1
SAA7388
DECEN 0 1 1 1 1 1 1 Note
1. Where X = don't care. 7.7.13 CTRL1
The reset function clears all the flags in this register. Table 8 BIT 7 6 5 CTRL1 register bits NAME SYIEN SYDEN DSCREN FUNCTION Disable sync interpolation = 0; Enable sync interpolation = 1. Enabling SYIEN prevents loss of synchronization when an error occurs in a sync pattern during data read. Disable sync detection = 0; Enable sync detection = 1. Enabling SYDEN synchronizes the decoder with the sync pattern detected in the input data. Descramble disable (audio) = 0; Descramble enable = 1. This bit enables/disables descrambling. Setting this bit to logic 0 allows reading of raw data on disc, even audio signals. This bit should be set to logic 1 for CROM data. CRC with error correction disabled = 0; Detection errors are corrected = 1. This bit enables/disables rewriting of error bytes in the buffer during error correction. Setting the bit to logic 0 allows CRC checks without error correction. Mode 1 request = 0; Mode 2 request = 1. This bit discriminates Mode 1/Mode 2. Form 1 request = 0; Form 2 request = 1. This bit discriminates Mode 2/Form 1 and Mode 2/Form 2. Disable mode check function = 0; Enable mode check function = 1. If the mode specified in the mode byte does not correspond with the raw data mode bit and this bit is set to logic 1 then error correction and detection is disabled. Header data on registers Head0 to Head3 = 0; Sub-header data on registers Head0 to Head3 = 1. This bit toggles header and sub-header data between registers HEAD0 to HEAD3.
4
COWREN
3 2 1
MODRQ FORMRQ MBCKRQ
0
SHDREN
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7.14 STAT0
SAA7388
Resetting the chip clears all bits in this register. Table 9 BIT 7 6 STAT0 register bits NAME CRCOK ILSYNC FUNCTION Cyclic redundancy check not OK = 0; Cyclic redundancy check OK = 1. Set by the EDC in accordance with the results of the CRC check. Sync pattern detected at word count 0 to 1174 or 1176 onwards = 1. This bit is set to logic 1 if the sync pattern in the incoming data is detected between word counts 0 and 1174 or 1176 to infinity, and the decoder has been retimed. Due to the presence of the cache RAM, it is necessary to stop error correction also when long blocks have been detected. Sync pattern inserted by sync interpolator not coincident with data sync = 1. This bit is set to logic 1, if the word counter reaches 1175 and no sync pattern has been detected in the input data. It indicates that the sync interpolator circuit inserted a sync. With SYIEN = 0, no sync found. Data block size has been extended = 1. This bit is set to logic 1, if the sync interpolator was switched off, and if the sync interpolator indicated that sync insertion was necessary. This condition causes the block length to be extended. Reserved SBLK Short block indication = 1. This bit is set to logic 1 if the decoder is not retimed when a sync pattern is detected in an incorrect word location, and is ignored while the SYDEN bit is set to logic 0. One or more bytes of the block are flagged with C2 flags = 1. This bit is set to logic 1 if one or more bytes of the current block contain erasures as indicated by the C2PO input. Uncorrectable errors in block = 1. This bit is set to logic 1 when one or more bytes of the current block remain in error after the error correction process.
5
NOSYNC
4
LBLK
3 2
1
ERABLK
0
UCEBLK
7.7.15
STAT1
Resetting the chip clears all bits in this register. The bits in this register indicate the reliability of data in the HEAD0 to HEAD3 registers. Bits MINERR, SECERR, BLKERR and MODERR indicate errors in the minutes, seconds, frames and mode bytes in the header of the current block. Bits SH0ERR to SH3ERR indicate errors in the respective bytes in the sub-header. Table 10 STAT1 register bits BIT 7 MINERR BIT 6 SECERR BIT 5 BLKERR BIT 4 MODER BIT 3 SH0ERR BIT 2 SH1ERR BIT 1 SH2ERR BIT 0 SH3ERR
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7.16 STAT2
SAA7388
The bits MODE and FORM in this register indicate the mode, form and correction scheme of the current frame. Table 11 STAT2 register bits BIT 7 RMOD3 BIT 6 RMOD2 BIT 5 RMOD1 BIT 4 RMOD0 BIT 3 MODE BIT 2 FORM BIT 1 RFORM1 BIT 0 RFORM2
Table 12 MODE and FORM bits MODE 0 1 X FORM 0 0 1 Mode 1 Mode 2, Form 1 Mode 2, Form 2 or ECC correction impossible The RFORM2, RFORM1 bits contain a preview of the form bit for the next frame Table 13 RFORM2 and RFORM1 bits RFORM1 0 0 1 RFORM2 0 1 X Form 0 Form 1 error in form byte MEANING SETTING
The Mode bit is always copied from the CTRL1 register. The Form information is determined by the AUTORQ bit in the CTRL0 register. When this bit is set to logic 0, the Form information is copied from the CTRL1 register. When this bit is set to logic 1 the Form information is copied from the Mode header byte. If correction of the block was impossible, FORM will be set to logic 1 regardless of the requested correction. This will happen under the following circumstances: * An illegally synchronized block (ILSYNC = 1 or LBLK = 1) * A data block specified as Mode 2, Form 2, or detected as Mode 2, Form 2 * A Mode 2 submode byte error detected during processing * A mode mismatch detected by the mode check function (MCHQRQ = 1) * A mode byte error detected by the mode check function (MCHQRQ = 1).
The RMOD3, RMOD2, RMOD1 and RMOD0 bits contain a preview of the next block MODE byte. RMOD3 = bit7 # bit6 # bit5 # bit4 # bit3 # C2FLAG RMOD2 = bit2 # C2FLAG RMOD1 = bit1 # C2FLAG RMOD0 = bit0 # C2FLAG
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 14 RMOD bits RMOD3 0 0 0 0 0 0 0 0 1 Note 1. Where X = don't care. 7.7.17 STAT3 RMOD2 0 0 0 0 1 1 1 1 X RMOD1 0 0 1 1 0 0 1 1 X RMOD0 0 1 0 1 0 1 0 1 X
SAA7388
MEANING mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 mode > 7 or error in mode byte (note 1)
Reading this register clears any DECI interrupts. Table 15 STAT3 register bits BIT 7 NAME VALST MEANING Registers associated with decoder interrupt valid = 0; Registers invalid = 1. This bit is a valid/invalid flag for the registers related to the decoder interrupt. After decoder interrupt, the sub-CPU must read out of all decoder registers before VALST goes HIGH. - ECC not performed on current block = 0; ECC has been performed on current block = 1. This bit will go to logic 1 if ECC correction has been performed on the current block. - - -
6 5
- CBLK
2 1 0 7.7.18 RESET
- - -
Writing to this register resets the SAA7388 and initializes all of the registers. The data written determines the host mode of SAA7388. Table 16 RESET register bits BIT 7 BIT 6 BIT 5 reserved BIT 4 BIT 3 BIT 2 BIT 1 HSEL BIT 0
The HSEL bits in the RESET register set the host interface mode. After a hardware reset the HSEL bits become 111. The SAA7388 will then wait until the sub-CPU writes to the RESET register and selects the host mode. After hardware reset 3-statable pins will be 3-state unless HRD is driven LOW.
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 17 HSEL bits HSEL CONTENT BIT 2 0 0 0 0 BIT 1 0 0 1 1 others 7.7.19 SUB_L, SUB_H BIT 0 0 1 0 1 SELECTED HOST INTERFACE Sanyo ATAPI Oak unknown host reserved DESCRIPTION Sanyo compatible mode ATAPI Mode Oak compatible mode
SAA7388
all host bus pins 3-state, default after h/w reset for future enhancements
This 10-bit register specifies the memory address of the subcode data block. This address will always be in the first 1 kbyte of memory. 7.7.20 INCNF
This register is used to specify the configuration of the input data path. Table 18 INCNF register bits BIT 7 6 NAME IISmode div1(1) I2S-bus DESCRIPTION mode = 0; EIAJ serial interface mode = 1. If div1 and div0 = logic 0 then no oversampling (normal CDROM modes); If div1 = logic 0 and div0 = logic 1 then 2 times oversampling; If div1 = logic 1 and div0 = logic 0 then 4 times oversampling. If div1 and div0 = logic 0 then no oversampling (normal CDROM modes); If div0 = logic 1 and div1 = logic 0 then 2 times oversampling; If div1 = logic 0 and div1 = logic 0 then 4 times oversampling. Selection of Q-to-W input format. Logic 0 = V4 mode; logic 1 = EIAJ mode. Q-to-W interface enable. Logic 0 = off; logic 1 = on. Q-to-W interface cooking enable. Logic 0 = cooked mode; logic 1 = RAW mode. External RAM test mode. Logic 0 = normal operation; logic 1 = RAM test mode. -
5
div0(1)
4 3 2 1 0 Note
QWmode QWon QWcook RAMtest -
1. For subcode Q-to-W recovery, the BCK clock is used as a timing reference. It is possible to recover the Q-to-W subcode using the SAA7388, while at the same time the serial interface is programmed in oversampling mode for a DAC. Under such circumstances, it is necessary to tell the SAA7388 the oversampling factor.
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7.21 MEMS
SAA7388
This register is used to specify the configuration of the external buffer memory. Table 19 MEMS register bits BIT 7 6 5 4 3 PRIORITY PRIORITY - RFRSH - DRAM refresh rate. Setting this bit specifies a DRAM refresh rate of clock frequency/400. Clearing this bit specifies a rate of clock frequency/200. WIth a 33 MHz clock this bit should be set, while with a 16 MHz clock the bit should be clear. DRAM width select. This bit should be set if the external DRAM has a nibble wide data bus. If the data bus is byte wide then this bit should be clear. SRAM/DRAM select. If the external buffer memory is DRAM then this bit should be cleared. If the memory is SRAM this bit should be set. CACHE memory select. If the internal cache is available then this bit should be clear. Setting this bit to logic 1 indicates that there is no internal cache memory. Host priority access. These bits specify the external memory accesses priority. NAME DESCRIPTION
2 1 0
WIDTH STATIC CACHE
Table 20 Host priority access PRIORITY BITS ACCESS BIT 6 0 0 1 1 BIT 5 0 1 0 1 only one host access has highest priority two successive host accesses have highest priority three successive host accesses have highest priority four successive host accesses have highest priority
7.7.22
ITRG
In the ATAPI mode writing to this register generates a host interrupt. This interrupt is cleared when the host reads the ATAPI status register or writes to the ATAPI command register. In the Sanyo and Oak compatibility modes writing to this register has no effect. 7.7.23 ASTAT
Bit 7 of this register is the BSY bit and this is set by the SAA7388 whenever; * SAA7388 is the selected drive and the host writes to the command register (ACMD) * The host writes the execute drive diagnostic command (90H) to the command register * The host writes to the device control register (ADCTR) and sets the SRST bit * There is a hardware reset. On reset this register is set to (80H).
This write only register is only available in the ATAPI mode; it is the ATAPI status register and is used to transfer status information to the ATAPI host.
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.7.24 ACMD 7.7.25 ADRADR
SAA7388
This read only register is only available in the ATAPI mode; it is the ATAPI command register and is used to transfer commands from the host to the SAA7388. The CMDI interrupt is generated when; * The host writes to this register while the SAA7388 is the selected drive (the DRV bit in the ADRSEL register is equal to the RDRV bit in the DTCTR register) * The host writes the execute drive diagnostic command (90H) to this register. The BSY bit in the ASTAT register is also set under these conditions. If the sub-CPU reads this register while CMDI is asserted then it will be negated. 7.7.28 ADRSEL
This write only register is the ATAPI Drive Address register. 7.7.26 ASAMT
This register is the ATAPI Sector Number register. 7.7.27 ADCTR
This read only register is the ATAPI Device Control register. If the SRSTI interrupt is asserted then reading this register will negate it.
Table 21 ADRSEL register bits BIT 7 1 BIT 6 1 BIT 5 1 BIT 4 DRV BIT 3 - BIT 2 - BIT 1 - BIT 0 -
Bit 4 of this register is the DRV bit. When this bit is the same as the RDRV bit in the DTCTR register then the SAA7388 will be the selected ATAPI drive and will respond to host commands and produce host interrupts. 7.7.29 AINTR 7.7.32 DTCTR - DATA TRANSFER CONTROL REGISTER
This register is the ATAPI Interrupt Reason register. 7.7.30 AFEAT
This read only register is the ATAPI Features register. 7.7.31 AERR
The DTCTR register controls data transfer flows in the host Interface block. On reset this register is cleared to all zeros except for the RDRV bit which is set to logic 1. This means that the SAA7388 will be set to drive 1 after a reset. There are several possible data transfers through the SAA7388 host Interface block and these are selected using the TRANT bits. The transfers are described in the Table 23.
This write only register is the ATAPI Error register.
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 22 Data transfer control register bits BIT 7 6 5 4 3 2 1 0 Table 23 TRANT transfer bits TRANT FROM BIT 2 0 0 0 0 1 1 1 BIT 1 0 0 1 1 0 0 1 BIT 0 0 1 0 1 0 1 x memory host sub-CPU memory host sub-CPU reserved host memory memory sub-CPU sub-CPU host reserved 65535 (ATAPI) 32767 (Sanyo) 65535 (ATAPI) 32767 (Sanyo) - - 12 12 reserved - - TO MAXIMUM BYTES FLAG res. DMAMODE UDMA SUBIEN RDRV TRANT Use DMA SUBI Enable Real Drive Select - VERBOSE - DMA Mode Select reserved logic 0 = single-word; logic 1 = multi-word logic 1 = DMA; logic 0 = PIO logic 1 = interrupt enabled ATAPI drive number see Table 23 DESCRIPTION
SAA7388
NOTES DMA and PIO DMA and PIO
PIO; DBC not used, always 12 bytes DMA and PIO -
In the Sanyo and Oak compatibility modes the only transfers are memory-to-host, host-to-memory, sub-CPU-to-memory, and memory-to-sub-CPU. Setting the TRANT bits to any other settings while in these host modes will cause undefined results.
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.8 Sub-CPU interface
SAA7388
The sub-CPU interface is a 3-wire synchronous serial protocol. The interface uses three signals; SYN is used as a synchronization signal, SDA is the bidirectional open-collector data signal and SCL is the bit clock. The start of a command is signalled by a pulse on the SYN input. After this pulse an 8-bit address byte will be sent by the sub-CPU. The format of this address byte is given in Table 24. Table 24 Address byte format BIT 7 6 NAME device select address mode DESCRIPTION If this bit is clear then the command will be for the SAA7388 otherwise the command is for another device and the SAA7388 will not respond. This bit controls the auto-increment function. After every byte has been read from or written to the SAA7388 the address register is updated so that it is not necessary to re-send the address to read or write the following byte. The way the address register is updated is determined by the address mode bit. If the address mode bit is logic 0 then the address register will increment by 1 if it is currently in the range 1 to 14 or 16 to 30. If the address register is currently 15 or 31 then it will update to 0, if the address register is at logic 0 then it will remain at address 0. If the address mode bit is logic 1 then the address register will update in the following sequences; Read: APCMD/COMIN -> APCMD/COMIN, IFSTAT -> DBCL -> DBCH -> HEAD0 -> HEAD1 -> HEAD2 -> HEAD3 -> PTL -> PTH -> PTHH -> WAL -> WAH -> WAHH -> STAT0 -> STAT1 -> STAT2 -> STAT3 -> APCMD/COMIN, ACMD -> ASMAT -> ADCTR -> ADRSEL -> AINTR -> AFEAT -> APCMD/COMIN. Write: ADATA/SBOUT -> ADATA/SBOUT, IFCTRL -> DBCL -> DBCH -> DACL -> DACH -> DACHH -> DTRG -> DTACK -> WAL -> WAH -> WAHH -> CTRL0 -> CTRL1 -> PTL -> PTH -> PTHH -> SUB_L ->SUB_H -> 21 -> INCNF -> MEMS -> ASTAT -> ITRG -> ADRADR -> ASAMT -> DTCTR -> ADRSEL -> AINTR -> AERR -> ADATA/SBOUT. 5 4 3 2 1 0 R/W If this bit is set to logic 0 then the sub-CPU will send one or more data bytes after the address byte. This data will be loaded into the specified registers. If this bit is set to logic 1 then after sending the address byte the sub-CPU will clock out the contents of one or more registers. register number This is the address that is loaded into the address register and determines which register is accessed.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
SYN
SCL SDA (from sub-CPU)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
READ/WRITE = 0
SYN
SCL SDA (from sub-CPU) SDA (from ELM) READ/WRITE = 1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
MGE191
Fig.3 Sub-CPU interface R/W timing diagram.
7.9 7.9.1
Host registers SANYO COMPATIBILITY MODE
Table 25 Sanyo compatibility mode HEN 0 0 0 0 1 Note 1. Where X = don't care. CMD 0 0 1 1 X HRD 1 0 1 0 X HWR 0 1 0 1 X write COMIN read SBOUT write data read data none (note 1) OPERATION
7.9.1.1
COMIN
This is a 12-byte FIFO used for sending commands from the host to the sub-CPU. When the host writes to the COMIN register a sub-CPU CMDI interrupt is generated to indicate there are bytes in the COMIN FIFO. This is cleared when the sub-CPU empties the FIFO. If the host writes to the register when the FIFO is full then the command is ignored.
If the host writes to this register when the CMDBK bit in the IFCTRL register is asserted then this will terminate any data or status byte transfers that are in progress.
7.9.1.2
SBOUT
This is a 12 byte FIFO used to transfer status bytes from the sub-CPU to the host. The host should only access this register when the STEN pin is LOW indicating that there are status bytes available.
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.9.1.3 Data Transfer
SAA7388
The other registers are used for data transfers. These can only occur when the sub-CPU has enabled a data transfer. This will be indicated to the host by the DTEN pin being LOW. 7.9.2 OAK COMPATIBILITY MODE
Table 26 Oak compatibility mode DMACK 1 1 1 1 1 1 1 1 0 0 Note 1. Where X = don't care. Data transfer is selected when the transfer type is non-DMA, the sub-CPU has started a data transfer and the DTS bit in the HCON register has not been asserted. DMA transfer is selected using the HCON register. The COMIN and SBOUT registers are similar to the same registers in the Sanyo compatibility mode. HEN(1) 0 0 0 0 0 0 0 1 X X DA1(1) 0 0 0 0 0 0 1 X X X DA0(1) 0 0 0 0 1 1 0 X X X HRD(1) 1 0 1 0 1 0 1 X 1 0 HWR(1) 0 1 0 1 0 1 0 X 0 1 DATA TRANSFER SELECTED(1) NO NO YES YES X X X X X X OPERATION write COMIN read SBOUT write data read data RESET sub-CPU read TSTAT write HCON none write DMA data read DMA data
7.9.2.1
RESET Sub-CPU
Writing to this register causes the SCRST pin to go LOW for several clock periods. The SAA7388 registers are not affected.
7.9.2.2
TSTAT
Table 27 TSTAT register bits BIT 7 1 BIT 6 1 BIT 5 EJECT BIT 4 WAIT BIT 3 EOP BIT 2 STEN BIT 1 DTEN BIT 0 DRQ
This is the host Transfer Status Register. The EJECT bit reflects the state of the EJECT pin. Bits EOP, STEN and DTEN have the same operation as the equivalent pins in the Sanyo compatibility mode. Bit WAIT is the same as the Sanyo mode WAIT pin when non-DMA transfer is selected otherwise it is logic 1. Bit DRQ is the same as the Sanyo mode WAIT pin when DMA transfer is selected otherwise it is logic 0.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.9.2.3 HCON
SAA7388
Table 28 HCON register bits BIT 7(1) X Note 1. Where X = don't care. This is the host configuration register. Resetting SAA7388 clears this register. Bit DTS is the suspend transfer bit. Setting this bit HIGH suspends non-DMA transfers and allows the host to access the COMIN and SBOUT registers. During DMA transfers this bit has no effect. If SDRQ is LOW and the SELRQ pin is LOW then DMA transfer is selected otherwise non-DMA transfer is selected. The pseudo 16-bit DMA read transfer is selected by setting bit DMA16 HIGH. DMA transfer must also be selected for this mode to operate. host writes are always 8-bit and are not affected by this bit. Table 29 ATAPI registers ADDRESS WRITE HWR CS2 1 1 1 1 1 1 1 1 0 0 CS1 0 0 0 0 0 0 0 0 1 1 DA2 0 0 0 0 1 1 1 1 1 1 DA1 0 0 1 1 0 0 1 1 1 1 DA0 0 1 0 1 0 1 0 1 0 1 DATA AFEAT AINTR ASAMT DBCL DBCH ADRSEL ACMD ADCTR reserved DATA AERR AINTR ASAMT DBCL DBCH ADRSEL ASTAT Alt Status ADRADR 16 8 8 8 8 8 8 8 8 8 READ HRD WIDTH The LOHI bit when HIGH causes the pseudo 16-bit DMA transfer to be a LOW byte followed by a HIGH byte. Setting it LOW causes the sequence to be a HIGH byte followed by a LOW byte. If the 16-bit DMA mode is not selected then this bit has no effect. 7.9.3 ATAPI MODE BIT 6(1) X BIT 5(1) X BIT 4(1) X BIT 3 DTS BIT 2 SDRQ BIT 1 LOHI BIT 0 DMA16
The following registers are accessible by the ATAPI host. Most of these registers are identical to the sub-CPU registers with the same name.
1996 Apr 26
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Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
Table 30 Description of registers REGISTER DATA AFEAT AERR AINTR ASAMT DBCL and DBCH ADRSEL DESCRIPTION
SAA7388
This is a 16-bit register and is used for transferring data to and from the host. This should only be performed after the Sub-CPU has initiated the data transfer. This is the ATAPI Features register. This is the ATAPI Error register. This is the ATAPI Interrupt Reason register. This is the ATAPI Sector Count register. These are the ATAPI Byte Count registers. This is the ATAPI Drive Select register (see Table 31). Bit 4 of this register is the DRV bit. When this bit is the same as the RDRV bit in the DTCTR register then SAA7388 will be the selected ATAPI drive and will respond to commands and produce interrupts. The host Interrupt pin will also be enabled when SAA7388 is the selected drive. This is the ATAPI Command register. A CMDI interrupt is generated when the host writes to this register while SAA7388 is the selected drive (the DRV bit in ADRSEL is equal to the RDRV bit in DTCTR) and when the host writes the execute drive diagnostic command (90H) to this register. If a host interrupt is asserted then it will be cleared by writing to this register. This is the ATAPI Status register. Bit-7 is the BSY bit and this will be set whenever the host writes to the ACMD register and SAA7388 is the selected drive, when the host writes the execute drive diagnostic command (90H) to the ACMD register, when the host writes to the ADCTR register and sets the SRST bit and when there is a hardware reset. If a host interrupt is asserted then it will be cleared by writing to this register.
ACMD
ASTAT
ALT STATUS This is the ATAPI Alternative Status register. This is identical to the ASTAT register except reading this register does not negate the host interrupt. ADCTR ADRADR This is the ATAPI Device Control register (see Table 32) This is the ATAPI Drive Address register. Bit 7 of this register is high impedance.
Table 31 ADRSEL register bits BIT 7 1 BIT 6 1 BIT 5 1 BIT 4 DRV BIT 3 - BIT 2 - BIT 1 - BIT 0 -
Table 32 ADCTR register bits BIT 7 BIT 6 reserved BIT 5 BIT 4 BIT 3 1 BIT 2 SRST BIT 1 nIEN BIT 0 0
Setting the SRST bit HIGH causes a SRSTI interrupt and the BSY bit to be set. Bit nIEN is used to enable or disable the host interrupt. When nIEN is logic 0 and the drive is selected then the host interrupt pin will be enabled. If nIEN is logic 1 or the drive is not selected then the host interrupt pin will be in a high-impedance state.
1996 Apr 26
29
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
7.10 CD-DSP Timings
SAA7388
The timings are for 8 times speed with a 33 MHz crystal.
handbook, full pagewidth
tPO tLC BCK tST WS DATA
MGE192
tHC
tHT
Fig.4 CD-DSP Interface Timing.
1996 Apr 26
30
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BCK DATA 0 15 LEFT CHANNEL DATA WS 0 15 C2PO LSB ERROR MSB ERROR LSB ERROR MSB ERROR
MGE193
Philips Semiconductors
Error correction and host interface IC for CD-ROM (ELM)
C2PO is sampled coincident with bits 14 and 12 of the incoming DATA.
Fig.5 Philips I2S-bus data format. 31
BCK DATA 0 15 RIGHT CHANNEL DATA WS 0 15 C2PO LSB ERROR MSB ERROR LSB ERROR MSB ERROR
MGE194
Preliminary specification
SAA7388
C2PO is sampled coincident with bits 14 and 12 of the incoming DATA.
Fig.6 EIAJ data format.
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD1 VDDD2 VI(max) VO IO IIK Pdiss Tstg Tamb Note 1. All VDD and VSS connections must be made externally to the same associated power supply. 9 THERMAL CHARACTERISTICS SYMBOL Rthj-a DESCRIPTION thermal resistance from junction to ambient in free air VALUE 55 PARAMETER digital supply voltage 1 digital supply voltage 2 maximum input voltage on any input output voltage on any output output current (continuous) DC input diode current (continuous) power dissipation storage temperature operating ambient temperature CONDITIONS note 1 note 1 MIN. -0.5 -0.5 -0.5 -0.5 - - - -55 0 MAX. +4.5 +6.5 VDDD + 0.5 +6.5 20 20 400 +125 +70
SAA7388
UNIT V V V V mA mA mW C C
UNIT K/W
1996 Apr 26
32
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
10 CHARACTERISTICS VDDD1 = 3.0 to 3.6 V; VDDD2 = 4.5 to 5.5 V; VSSD = 0; Tamb = 0 to 70 C; unless otherwise stated. SYMBOL Supply VDDD1 VDDD2 IDDD IDDDq digital supply voltage 1 digital supply voltage 2 supply current quiescent supply current VDDD1 = 3.3 V; VDDD2 = 5 V VDDD1 = 3.3 V; VDDD2 = 5 V 3.0 4.5 - - 3.3 5.0 60 100 3.6 5.5 - - PARAMETER CONDITIONS MIN. TYP.
SAA7388
MAX.
UNIT
V V mA mA
Digital inputs INPUT: RESET (CMOS INPUT) Vth(r) Vth(f) Vhys Ci tRW switching threshold rising switching threshold falling hysteresis voltage input capacitance RESET pulse width RESET only - 0.2VDDD2 - - 1 - - 0.33VDDD2 - - 0.8VDDD2 - - 10 - V V V pF s
INPUTS: SFSY, SUB, BCK, WS, DATA, C2PO, SCL, CS1/HEN, HWR, HRD, DA0/CMD, DMACK/SELRQ, DA1, DA2/EJECT, CS2 AND SYN (CMOS INPUT) VIL VIH ILI Ci VIL VIH Rpd Ci LOW level input voltage HIGH level input voltage input leakage current input capacitance Vi = 0 - VDDD2 -0.3 0.7VDDD2 -10 - -0.3 0.7VDDD2 Vi = VDDD2 - - - - - - - - 50 - 0.3VDDD2 +10 10 V A pF VDDD2 + 0.3 V
INPUTS: TEST1 AND TEST2 (CMOS INPUT) LOW level input voltage HIGH level input voltage input pull-down resistance input capacitance 0.3VDDD2 VDDD2 + 0.3 - 10 V V k pF
Digital outputs OUTPUTS: RA0, RA1 TO RA14, RA15/RAS, RA16/CAS, RWE, RCK AND SCRST/STEN VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time CL = 20 pF; 0.8 to (VDDD2 - 0.8) CL = 20 pF; (VDDD2 - 0.8) to 0.8 IOL = 1 mA IOH = -1 mA 0 - - - - - - - 0.4 VDDD2 25 10 10 V V pF ns ns VDDD2 - 0.4 -
1996 Apr 26
33
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL PARAMETER CONDITIONS MIN. - - - - TYP.
SAA7388
MAX.
UNIT
OPEN-DRAIN OUTPUTS; INT, IOCS16 VOL IOL CL tf LOW level output voltage LOW level output current load capacitance output fall time CL = 20 pF; 0.8 - (VDDD2 - 0.8) VDDD2 = 4.5 to 5.5 V; IOL = 1 mA 0 - - - 0.4 2 25 20 V mA pF ns
3-state outputs OUTPUTS: IRQ/EOP/HFBC, IORDY/WAIT/HFBLB AND DMARQ/DTEN VOL VOH CL tr tf ILZ LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; 0.8 - (VDDD2 - 0.8) CL = 20 pF; (VDDD2 - 0.8) - 0.8 Vi = 0 - VDDD2 IOL = 1 mA IOH = -1 mA 0 - - - -10 - - - - - 0.4 VDDD2 50 15 15 +10 V V pF ns ns A VDDD2 - 0.4 -
Digital inputs/outputs INPUTS AND OUTPUTS: RD0 TO RD7 VOL VOH VIL VIH CL tr tf ILZ VOL VOH VIL VIH CL tr tf ILZ LOW level output voltage HIGH level output voltage LOW level input voltage HIGH level input voltage load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; 0.8 - (VDDD2 - 0.8) CL = 20 pF; (VDDD2 - 0.8) - 0.8 Vi = 0 - VDDD2 IOL = 1 mA IOH = -1 mA IOL = 1 mA IOH = -1 mA 0 -0.3 0.7VDDD2 - - - -10 0 -0.3 0.7VDDD2 - CL = 20 pF; 0.8 - (VDDD2 - 0.8) CL = 20 pF; (VDDD2 - 0.8) - 0.8 Vi = 0 - VDDD2 - - -10 - - - - - - - - - - - - - - 0.4 VDDD2 0.3VDDD2 50 15 15 +10 V V V pF ns ns A V V V pF ns ns A VDDD2 - 0.4 -
VDDD2 + 0.3 V
INPUTS AND OUTPUTS: HD0 TO HD15 LOW level output voltage HIGH level output voltage LOW level input voltage HIGH level input voltage load capacitance output rise time output fall time 3-state leakage current 0.4 VDDD2 0.3VDDD2 100 5 5 +10 VDDD2 - 0.4 -
VDDD2 + 0.3 V
1996 Apr 26
34
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL PARAMETER CONDITIONS MIN. -0.3 0.7VDDD2 Vi = 0 - VDDD2 IOL = 1 mA IOH = -1 mA -10 - 0 - - CL = 25 pF; 0.8 - (VDDD2 - 0.8) CL = 25 pF; (VDDD2 - 0.8) - 0.8 - - - - - - - - - - - TYP.
SAA7388
MAX.
UNIT
INPUT AND OUTPUT: SDA VIL VIH ILZ Ci VOL VOH IOL CL tr tf LOW level input voltage HIGH level input voltage 3-state leakage current input capacitance LOW level output voltage HIGH level output voltage LOW level output current load capacitance output rise time output fall time 0.3VDDD2 +10 10 0.4 VDDD2 4 100 5 5 V A pF V V mA pF ns ns VDDD2 + 0.3 V
VDDD2 - 0.4 -
Crystal oscillator INPUT: CRIN (EXTERNAL CLOCK) ILI Ci fxtal gm RO Cfb Co input leakage current input capacitance -10 - 15.2 - - - - - - 48 4 11 - - +10 10 A pF
OUTPUT: CROUT crystal frequency mutual conductance at start-up output resistance at start-up feedback capacitance output capacitance 50.4 - - 5 10 MHz mA/V k pF pF
1996 Apr 26
35
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11 TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7388
MAX.
UNIT
CD-DSP timing; see Figs 4, 5 and 6; note 1 INPUT: BCK tPO tHC tLC tST tHT input clock period clock HIGH time clock LOW time 40 14 14 - - - - - 1050 - - - - ns ns ns
INPUTS: WS AND DATA set-up time hold time 8 0 ns ns
Q-to-W subcode timing; see Figs 7 and 8; note 1 INPUT: SFSY tFW tF tLW tHW tCD tHPW tLPW INPUT: SUB tHD tAC tPAC tRC tDS tDH tWC tWP tAS tWR tDO data hold time data access time P data access time 0 - - - - 2 - - - - - - - - - 0.8 4 - - - - - - - 30 s s s sync pulse width frame cycle LOW level period HIGH level period 244 122 1.5 4 272 136 68 68 800 150 - - 30 6 9 s s s s s s s
OUTPUT: RCK output delay time HIGH level period LOW level period 5 0.6 2 20 4 4
SRAM interface timing; see Figs 9 and 10; note 2 read cycle period data set-up time data hold time write cycle time write pulse time address set-up time write recovery time data output time 6T 30 5 6T 2T T T - ns ns ns ns ns ns ns ns
1996 Apr 26
36
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SAA7388
MAX. - - 3T - 10 7T - 10 - - 4T - - - - - - - - - - - - - - - - - - - - - - - - - - 400T 800T - - -
UNIT
DRAM interface timing; see Figs 11 and 12; note 2 tRC tPC tCAC tRAC tOFF tRHCP tCAA tRP tRAS tRSH tCAS tCSH tCP tCRP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWP tWCR tCWL tRWL tDS tDH tDHR tRFSH tCSR tCHR tRPC 1996 Apr 26 read or write cycle period page mode cycle time access time from CAS access time from RAS output disable time from CAS RAS hold time from CAS precharge page mode column address access RAS HIGH time RAS LOW time RAS hold time CAS LOW time CAS hold time CAS HIGH pulse width delay CAS HIGH to RAS RAS to CAS delay time RAS to column address delay row address set-up time row address hold time column address set-up time column address hold time column address hold time from RAS LOW column address to RAS lead read set-up time before CAS read command hold time read command hold time from RAS write command hold time write command LOW time write command hold time from RAS write command to CAS lead write command to RAS lead data output set-up time data output hold time data output hold from RAS refresh cycle time CAS set-up time for refresh CAS hold time for refresh precharge to CAS active time 37 MEMS(3) = 0 MEMS(3) = 1 10T 4T - - 0 4T - 4T 6T 4T - 10 3T 7T - 10 T 3T - 10 2T T 3T - 10 T T 3T - 10 5T - 10 3T 4T - 10 T 2T - 10 6T - 10 10T 8T - 10 9T - 10 8T - 10 T 3T 7T - 10 - - 2T - 10 6T - 10 T ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - -
SAA7388
MAX. - - - - - 150
UNIT
Sub-CPU timing; see Fig.13 t0 t1 t2 t3 t4 t5 syn to first SCL SCL cycle time time between bytes data set-up data hold data access 250 500 250 150 0 - ns ns ns ns ns ns
ATAPI host interface timing; see Fig.14 PIO 8 AND 16-BIT TRANSFER t0 t1 t2 t2i t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t0 t1 t2 t3 t4 t5 t6 t7 t8 cycle time address to HWR/HRD set-up HWR/HRD active HWR/HRD inactive HWR data set-up HWR data hold HRD data set-up HRD data 3-state address to IOCS16 address to IOCS16 negate HWR/HRD to address hold IORDY set-up IORDY width read data valid to IORDY active only if IORDY negated only if IORDY negated only for 16-bit data register only for 16-bit data register 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 150 240 30 80 100 70 140 30 10 50 - - - 10 - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 30 30 - 35 1250 - - - 80 - - - - - - 60 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SINGLE-WORD DMA TRANSFER; see Fig.15 cycle time DMACK to DMARQ DMACK to HWR/HRD HWR/HRD active HWR/HRD to DMACK hold HWR data set-up HWR data hold HRD data access HRD data hold 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 240 480 - 0 120 240 0 35 20 - 5 ns ns ns ns ns ns ns ns ns ns ns
1996 Apr 26
38
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - - - - - - -
SAA7388
MAX. - 40 - - - - - - 60 - 25
UNIT
MULTI-WORD DMA TRANSFER; see Fig.16; note 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 cycle time HWR/HRD to DMARQ inactive DMACK to HWR/HRD HWR/HRD active HWR/HRD inactive HWR/HRD to DMACK hold HWR data set-up HWR data hold HRD data access HRD data hold DMACK inactive to read data 3-state 130 - 0 80 50 5 30 15 - 5 - ns ns ns ns ns ns ns ns ns ns ns
Sanyo compatibility mode host interface timing; see Fig.17 COMIN AND SBOUT ACCESS t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 HEN set-up HEN hold CMD set-up CMD hold HWR/HRD active HWR/HRD data inactive HWR data set-up HWR data hold HRD data access HRD data to 3-state STEN to HRD HRD to STEN inactive only for SBOUT read for last SBOUT read; 33 MHz clock 16 MHz clock t12 HWR to DTEN/STEN inactive only for COMIN write when CMDBK = 0 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 30 0 15 5 50 75 60 145 50 20 - 5 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 60 - 100 145 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Apr 26
39
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SAA7388
MAX. - - - - - - - - - - 80 60 80 - 100 145 120 120 - - - - - - - - - - 80 60 - 80 - 100 145 120
UNIT
WAIT CONTROL DATA TRANSFER; see Fig.18 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 HEN set-up HEN hold CMD set-up CMD hold HWR/HRD active HWR/HRD inactive HWR data set-up HWR data hold HRD data access HRD data to 3-state HWR/HRD to WAIT active DTEN to HWR/HRD HWR/HRD to DTEN inactive for last data transferred; 33 MHz clock 16 MHz clock t13 t14 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 HWR/HRD to EOP only for last data access HWR/HRD inactive to EOP inactive only for last data access 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 30 0 15 5 50 75 60 145 50 20 - 5 - 0 - - - - 30 0 15 5 33 MHz clock 16 MHz clock HWR/HRD data inactive HWR data set-up HWR data hold HRD data access HRD data to 3-state DRQ to HWR/HRD HWR/HRD to DRQ inactive DTEN to HWR/HRD HWR/HRD to DTEN inactive for last data transferred; 33 MHz clock 16 MHz clock t14 HWR/HRD to EOP only for last data access 33 MHz clock 16 MHz clock 50 75 60 145 50 20 - 5 0 - 0 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DRQ CONTROL DATA TRANSFER; see Fig.19 HEN set-up HEN hold CMD set-up CMD hold HWR/HRD active ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Apr 26
40
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL t15 PARAMETER CONDITIONS - MIN. TYP. -
SAA7388
MAX. 120
UNIT ns
HWR/HRD inactive to EOP inactive only for last data access
Oak compatibility mode host interface timing; see Fig.20 COMIN, HCON WRITE AND SBOUT, TSTAT READ t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 t6 HEN set-up HEN hold DMACK set-up DMACK hold address set-up address hold HWR/HRD active HWR/HRD inactive HWR data set-up HWR data hold HRD data access HRD data to 3-state 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 30 0 30 0 30 0 50 75 60 145 50 20 - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 80 60 - - - - - - - - - - 100 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RESET SUB-CPU; see Fig.21; note 4 HEN set-up HEN hold DMACK set-up DMACK hold address set-up address hold HWR active HWR inactive HWR to SCRST HWR inactive to SCRST inactive 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 30 0 30 0 30 0 50 65 60 145 - 512CLK ns ns ns ns ns ns ns ns ns ns ns ns
NON-DMA DATA TRANSFER; see Fig.22; note 4 HEN set-up HEN hold DMACK set-up DMACK hold address set-up address hold HWR/HRD active 33 MHz clock 16 MHz clock 30 0 30 0 30 0 50 75 ns ns ns ns ns ns ns ns
1996 Apr 26
41
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SYMBOL t7 t8 t9 t10 t11 t12 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Notes 1. All timings are for single-speed, they should be divided by the speed up to eight times speed. 2. T represents half a clock period. 3. The timings for this mode can only be met with a 33 MHz clock. 4. CLK = 1 clock period. PARAMETER HWR/HRD inactive HWR data set-up HWR data hold HRD data access HRD data to 3-state cycle time CONDITIONS 33 MHz clock 16 MHz clock 60 145 50 20 - 5 3CLK MIN. TYP. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SAA7388
MAX. - - - - 80 60 - - 80 - - - - - - - - 80 60
UNIT ns ns ns ns ns ns ns
8-BIT DMA DATA TRANSFER; see Fig.23 DMARQ to DMACK HWR/HRD to DMARQ inactive DMACK set-up DMACK hold HWR/HRD active HWR/HRD inactive HWR data set-up HWR data hold HRD data access HRD data to 3-state 33 MHz clock 16 MHz clock 33 MHz clock 16 MHz clock 0 - 30 0 50 75 60 145 50 20 - - - 0 0 33 MHz clock 16 MHz clock HFBC to data valid data 3-state to HFBC inactive HRD data access HRD data to 3-state HFBC active data valid to HFBLB HFBLB to HFBC inactive 50 65 - CLK - - - 2CLK 2CLK ns ns ns ns ns ns ns ns ns ns ns ns
PSEUDO 16-BIT DMA READ TRANSFER; see Fig.24; note 4 HRD to DMARQ inactive DMARQ to DMACK HRD inactive to DMACK inactive HRD active 80 - - - - CLK - 80 60 5CLK - - ns ns ns ns ns ns ns ns ns ns ns ns
1996 Apr 26
42
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11.1 Q-to-W subcode interface timing
SAA7388
handbook, full pagewidth
tFW
tF
tLW
tHW
SFSY
RCK
P Q R S T U VW
P Q R S T U VW
P Q R S T U VW
P Q R S T U VW
P Q R S T U VW
SUB SF97 SF0 SF1 SF2 SF3 SF4 SF5
MGE195
Fig.7 Q-to-W subcode interface timing diagram.
handbook, full pagewidth
SFSY tCD RCK tPAC tHD tAC tHD tAC tHD tLPW tHPW
SUB
MGE196
Fig.8 Q-to-W subcode timing diagram.
1996 Apr 26
43
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11.2 External memory SRAM timing
SAA7388
handbook, full pagewidth
tRC
ADDRESS
DATA tDS tDH
MGE197
Fig.9 Read cycle timing diagram
handbook, full pagewidth
tWC
ADDRESS tAS RWE tWP DATA tDO
MGE198
tWR
Fig.10 Write cycle timing diagram
1996 Apr 26
44
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11.3 External memory DRAM timing
SAA7388
handbook, full pagewidth
tRC tRAS tAR tRP
RAS tCSH tRCD tCRP CAS tASR tRAD tRAH RA0 to RA13 ROW tCAH COLUMN tWCH tWP RWE tWCR tRWL tCWL tDHR tDS RD0 to RD7
MGE199
tRSH tCAS tCRP
tASC tRAL
tDH
Fig.11 Write cycle timing diagram
1996 Apr 26
45
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
tRC tRAS tAR tRP
RAS tCSH tCRP tRCD tRSH tCAS tCRP
CAS tASR tRAD tRAH RA0 to RA13 ROW tRCS RWE tCAC RD0 to RD7 tRAC INPUT
MGE200
tASC tRAL tCAH COLUMN
tRCH tRRH
Fig.12 Read cycle timing diagram
1996 Apr 26
46
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11.4 Sub-CPU interface timing
SAA7388
handbook, full pagewidth
t0 SYN t1 t2
SCL
t3 SDA (sub-CPU to ELM) t5 SDA (ELM to sub-CPU) 0
t4 1 7
MGE201
Fig.13 Sub-CPU interface timing diagram. 11.5 ATAPI host interface timing
handbook, full pagewidth
t0 address t1 t9
t2
t2i
HWR/HRD t3 write data valid t5 read data valid t7 IOCS16 t12 t8 t6 t4
t10 IORDY valid
t11
MGE202
Fig.14 PIO 8 and 16-bit transfer.
1996 Apr 26
47
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
t0 DMARQ t1 DMACK t2 t3 t4
HWR / HRD t5 write data valid (HD0 to HD15) t6
t7
t8
read data valid (HD0 to HD15)
MGE203
Fig.15 Single-word DMA transfer.
handbook, full pagewidth
t0
DMARQ t1 DMACK t2 HWR/HRD t6 write data valid (HD0 to HD15) t8 read data valid (HD0 to HD15)
MGE204
t3
t4
t5
t7
t9
t10
Fig.16 Multi-word DMA transfer.
1996 Apr 26
48
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11.6 SANYO compatibility mode host interface timing
SAA7388
handbook, full pagewidth
t0 HEN t2 CMD t4 HWR/HRD t6 COMIN write (HD0 to HD7) t8 SBOUT read (HD0 to HD7) t10 STEN (SBOUT read) t12 STEN/DTEN (CMDBK = 0, COMIN write) t11 t9 t7
t1
t3
t5
MGE205
Fig.17 COMIN and SBOUT access.
1996 Apr 26
49
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
t0 HEN t2 CMD t4 HWR/HRD t6 write data valid (HD0 to HD7) t8 read data valid (HD0 to HD7) t10 WAIT t11 DTEN
t1
t3
t5
t7
t9
t12
t13 EOP
MGE206
t14
Fig.18 WAIT control and data transfer.
1996 Apr 26
50
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
t0 HEN t2 CMD t4 HWR/HRD t6 write data valid (HD0 to HD7) t8 read data valid (HD0 to HD7)
t1
t3
t5
t7
t9
t10
t11
DRQ (wait) t12 DTEN t14 EOP
MGE207
t13
t15
Fig.19 DRQ control data transfer.
1996 Apr 26
51
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
11.7 Oak compatibility mode host interface timing
t0 HEN t2 DMACK t4 DA1 to DA0 t6 HWR/HRD t8 COMIN, HCON write t10 SBOUT, TSTAT read
MGE208
SAA7388
handbook, full pagewidth
t1
t3
t5
t7
t9
t11
Fig.20 COMIN, HCON write and SBOUT, TSTAT read.
handbook, full pagewidth
t0 HEN t2 DMACK t4 DA1 to DA0 t6 HWR
t1
t3
t5
t7
don't care write t8 SCRST
MGE209
t9
Fig.21 RESET sub-CPU.
1996 Apr 26
52
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
t0 HEN t2 DMACK t4
t1
t3
t5
DA1 to DA0 t6 HWR/HRD t8 write data valid (HD0 to HD7) t10 read data valid (HD0 to HD7) t12
MGE210
t7
t9
t11
Fig.22 Non-DMA data transfer.
handbook, full pagewidth
DMARQ t0 DMACK t2 t3 t1
t4
t5
HWR/HRD t6 write data valid (HD0 to HD7) t8 read data valid (HD0 to HD7) t9 t7
MGE211
Fig.23 8-bit DMA data transfer.
1996 Apr 26
53
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
SAA7388
handbook, full pagewidth
t0
DMARQ t1 DMACK
t2
t3 HRD t4 read data valid (HD0 to HD7) first byte t8 HFBC t9 HFBLB
MGE212
t5
t6
t7 last byte
t10
Fig.24 Pseudo 16-bit DMA read transfer.
11.8
Crystal oscillator
The crystal oscillator is a conventional 2 pin design operating at 15 to 50.4 MHz. This oscillator is also capable of operating with a ceramic resonator. It is capable of oscillating with both fundamental and third overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone types as illustrated in Fig.25.
handbook, halfpage SAA7388
OSCILLATOR CROUT 470 33 MHz 3rd overtone only 100 k 3.3 H 10 pF 10 pF 1 nF CRIN
MGD304
Fig.25 Crystal oscillator circuit.
1996 Apr 26
54
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
12 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7388
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1996 Apr 26
55
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
13 SOLDERING 13.1 Introduction
SAA7388
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). 13.3.2 SO
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 13.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP and SO packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 13.3 13.3.1 Wave soldering QFP
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 13.3.3 METHOD (QFP AND SO)
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Repairing soldered joints
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Apr 26
56
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7388
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Apr 26
57
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
NOTES
SAA7388
1996 Apr 26
58
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for CD-ROM (ELM)
NOTES
SAA7388
1996 Apr 26
59
Philips Semiconductors - a worldwide company
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All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
517021/1200/01/pp60 Document order number: Date of release: 1996 Apr 26 9397 750 00808

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